DocumentCode
3543049
Title
Probabilistic congestion prediction in hierarchical quad-grid model
Author
Yan, Jin-Tai ; Chen, Yen-Hsiang ; Wu, Chia-Wei
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Chung Hua Univ., Hsinchu, Taiwan
fYear
2005
fDate
23-26 May 2005
Firstpage
1350
Abstract
A probabilistic congestion prediction approach in a dynamic hierarchical quad-grid model is proposed to be applied in timing-constrained congestion-driven global routing (TCGR). Experimental results show that the TCGR algorithm (Yan, J.T. and Lin, S.H., Asia-Pacific Design Automation Conf., p.683-6, 2004) with the proposed probabilistic congestion prediction can use less CPU time to obtain a better timing-constrained congestion-driven global routing result for the tested benchmark circuits.
Keywords
VLSI; circuit layout CAD; integrated circuit layout; network routing; system-on-chip; CPU time; SOC design; VLSI circuits; benchmark circuits; congestion control; floorplan; hierarchical quad-grid model; probabilistic congestion prediction; timing-constrained congestion-driven global routing; Benchmark testing; Central Processing Unit; Chip scale packaging; Circuit testing; Computer science; Integrated circuit interconnections; Pins; Predictive models; Routing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464846
Filename
1464846
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