Reduced order modeling of coupled on-chip interconnects for silicon-based RF integrated circuits

Author

Ji Zheng ; Tripathi, V.K. ; Weisshaar, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA

Volume

2

fYear

2000

fDate

11-16 June 2000

Firstpage

973

Abstract

A reduced order modeling methodology of coupled on-chip interconnects for silicon-based RF integrated circuits is presented. The modeling approach is based on a mixed PEEC formulation combined with a hierarchical model order I reduction technique and captures both the conductor skin and proximity effects and the substrate skin effect. The response of the CAD-oriented macromodel is in good agreement with EM simulation results.

Keywords

CMOS integrated circuits; equivalent circuits; integrated circuit interconnections; integrated circuit modelling; reduced order systems; skin effect; CAD macromodel; CMOS technology; EM simulation; Si; coupled on-chip interconnect; hierarchical model; partial element equivalent circuit; proximity effect; reduced order model; silicon RF integrated circuit; skin effect; Conductors; Coupling circuits; Integrated circuit interconnections; Integrated circuit modeling; Proximity effect; Radio frequency; Radiofrequency integrated circuits; Silicon; Skin effect; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest. 2000 IEEE MTT-S International

Conference_Location

Boston, MA, USA

ISSN

0149-645X

Print_ISBN

0-7803-5687-X

Type

conf

DOI

10.1109/MWSYM.2000.863519

Filename

863519