DocumentCode
3543242
Title
Implementation of low-complexity FIR filters using serial arithmetic
Author
Johansson, Kenny ; Gustafsson, Oscar ; Wanhammar, Lars
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Sweden
fYear
2005
fDate
23-26 May 2005
Firstpage
1449
Abstract
The effects of digit-size on FIR filters implemented using multiplier block techniques are studied. Two different multiplier block algorithms are considered, one that minimizes the number of adders without considering the number of shifts and one that minimizes the number of shifts while keeping the number of adders low. Results on area, sample rate, and power consumption are presented, focusing on the arithmetic parts of the FIR filter.
Keywords
FIR filters; adders; digital arithmetic; logic design; minimisation; power consumption; adders; low-complexity FIR filters; minimization; multiplier block techniques; power consumption; sample rate; serial arithmetic; Arithmetic; Costs; Digital signal processing; Electronic mail; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Flip-flops; Flow graphs; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464871
Filename
1464871
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