Turbo decoder design for advanced T-DMB baseband receiver SoC

This paper presents a design of a turbo decoder for advanced terrestrial DMB(AT-DMB) baseband receiver SoC. The turbo decoder uses the max-log-map algorithm with simple min function. It features an interleaver address generator that computes the interleaved addresses for four block sizes enabling it to quickly switch context to support different data services. The decoder is integrated to the AT-DMB baseband receiver SoC with other functional blocks. The AT-DMB baseband receiver SoC is fabricated using 0.13 um 1 poly 8 metal technology.