DocumentCode
3543288
Title
Scaling directions for 2D and 3D NAND cells
Author
Goda, Akira ; Parat, K.
Author_Institution
Micron Technol., Boise, ID, USA
fYear
2012
fDate
10-13 Dec. 2012
Abstract
This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.
Keywords
NAND circuits; 2D NAND cells; 3D NAND cells; FG cell; planar floating gate cell; size 20 nm; Computer architecture; Conductivity; Interference; Logic gates; Noise; Reliability; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location
San Francisco, CA
ISSN
0163-1918
Print_ISBN
978-1-4673-4872-0
Electronic_ISBN
0163-1918
Type
conf
DOI
10.1109/IEDM.2012.6478961
Filename
6478961
Link To Document