Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology

Author

Kar, Gouri Sankar ; Breuil, L. ; Blomme, P. ; Hody, Hubert ; Locorotondo, S. ; Jossart, N. ; Richard, O. ; Bender, Hugo ; Van den bosch, G. ; Debusschere, I. ; Van Houdt, J.

Author_Institution

Imec, Leuven, Belgium

fYear

2012

fDate

10-13 Dec. 2012

Abstract

For the first time we demonstrate ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 nm with improved program performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacturability and scalability for high density memory application.

Keywords

NAND circuits; flash memories; high-k dielectric thin films; HFG thickness; IGD enabler; P-E cycling endurance; high density memory application; high-k dielectric; highly scaled planar NAND flash technology; manufacturability; post cycling data retention; program performance improvement; scalability; size 4 nm; ultra thin hybrid floating gate; Computer architecture; High K dielectric materials; Logic gates; Microprocessors; Nonvolatile memory; Silicon; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4673-4872-0

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2012.6478962

Filename

6478962