DocumentCode :
3543338
Title :
Downsizing and memory array integration of Pt/SrBi2Ta2O9/Hf-Al-O/Si ferroelectric-gate field-effect transistors
Author :
Sakai, Shin´ichi ; Xizhen Zhang ; Le Van Hai ; Wei Zhang ; Takahashi, Masaharu
Author_Institution :
Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
fYear :
2012
fDate :
Oct. 31 2012-Nov. 2 2012
Firstpage :
55
Lastpage :
59
Abstract :
First, fabrication and characterization of a NAND flash memory using novel memory cells of ferroelectric-gate field-effect transistors (FeFETs), which is named Fe-NAND, was reviewed. A 64 kb Fe-NAND memory cell array with bit-line- and block- selector circuits was produced and characterized. Several standard operations for a NAND flash memory were demonstrated. All-cell-erase, all-cell-program, and a checkerboard-pattern program showed a good “1” vs. “0” separation in their threshold-voltage distributions. Downsizing of the memory-cell FeFETs has been also progressed. The FeFET with the gate-length 0.26 μm showed high endurance by 109 cycles of 1±5 V-high and 10 μs-wide pulses imposed. Second, we also discussed our FeFET performance in comparison with the other HfO2-based nonvolatile FETs.
Keywords :
NAND circuits; aluminium; ferroelectric storage; field effect transistors; flash memories; hafnium; oxygen; platinum alloys; silicon; strontium compounds; Fe-NAND memory cell array; NAND flash memory; Pt-SrBi2Ta2O9-Hf-Al-O-Si; all cell erase; all cell program; checkerboard pattern program; ferroelectric gate field effect transistor downsizing; memory array integration; threshold voltage distribution; Arrays; Field effect transistors; Hafnium compounds; Logic gates; Nonvolatile memory; Silicon; Fe-NAND; FeFET; ferroelectric; flash memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Non-Volatile Memory Technology Symposium (NVMTS), 2012 12th Annual
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-2847-0
Type :
conf
DOI :
10.1109/NVMTS.2013.6632862
Filename :
6632862
Link To Document :
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