DocumentCode
3543365
Title
Modeling and test for parasitic resistance and capacitance defects in PCM
Author
Xiujuan Pan ; Xiaole Cui ; Jin Zha ; Xinnan Lin ; Chung Len Lee
Author_Institution
Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Beijing, China
fYear
2012
fDate
Oct. 31 2012-Nov. 2 2012
Firstpage
73
Lastpage
76
Abstract
Parasitic capacitance and resistance have much influence on the performance of the phase change memory (PCM). Based on SPICE circuit simulations, this paper investigates possible faults caused by the parasitic capacitance and resistance defects in stand-alone PCM cells. A realistic set of fault models are proposed and a test algorithm is proposed to test the faults.
Keywords
SPICE; capacitance; electric resistance; phase change memories; PCM; SPICE circuit simulations; capacitance defects; parasitic resistance; phase change memory; Circuit faults; Integrated circuit modeling; Parasitic capacitance; Phase change materials; Programming; Resistance; PCM; SPICE model; capacitance and resistance defects; fault model; test algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Non-Volatile Memory Technology Symposium (NVMTS), 2012 12th Annual
Conference_Location
Singapore
Print_ISBN
978-1-4673-2847-0
Type
conf
DOI
10.1109/NVMTS.2013.6632866
Filename
6632866
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