Comprehensive extensibility of 20nm low power/high performance technology platform featuring scalable high-k/metal gate planar transistors with reduced design corner

Extensibility of the high-k/metal gate (HK/MG) planar devices beyond 20nm node with high performance, low power consumption, less layout dependence and suppressed local variability were comprehensively studied among gate first (GF) and gate-last (GL) schemes for the first time. We demonstrated the N-/PFET drive current (Idsat) of 1.45/1.3 mA/μm with the off-leakage current (Ioff) of 100 nA/μm for the Vdd of 0.9V by scaling down the gate width (Wg) of GL-HK/MG devices to 60nm. Key layout dependence of the PFET with embedded SiGe source/drain (eSiGe) was improved by eSiGe interface engineering and scaling down the Wg with keeping the multiple threshold voltage (Vt) and improving the body-bias effect (BE). Moreover, we demonstrated reduction in the capacitance by conventional method even for such a scaled planar device. Finally, we achieved the sufficiently low Vt mismatch, which is required to reduce the design corner, by eSiGe interface engineering and reduction of interface states in the gate stack (Dit).