UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

Author

Grenouillet, L. ; Vinet, M. ; Gimbert, J. ; Giraud, Bastien ; Noel, J.P. ; Liu, Quanwei ; Khare, Priyank ; Jaud, M.A. ; Le Tiec, Y. ; Wacquez, R. ; Levin, T. ; Rivallin, P. ; Holmes, Sam ; Liu, Siyuan ; Chen, Kevin J. ; Rozeau, O. ; Scheiblin, P. ; Mclell

Author_Institution

CEA-LETI, Albany, NY, USA

fYear

2012

fDate

10-13 Dec. 2012

Abstract

We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune V_t by more than 400mV, that transistor performance can be boosted by up to 30% and that I_off can be controlled over 3 decades by allowing more than V_DD/2 to be applied on the back gate.

Keywords

MOSFET; silicon-on-insulator; PMOSFET; SOI substrates; UTBB FDSOI transistors; back bias; back gate; dual STI configuration; multivoltage strategy; size 20 nm; ultrathin body and box architecture; Doping; Implants; Junctions; Logic gates; Performance evaluation; Substrates; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4673-4872-0

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2012.6478974

Filename

6478974