Title :
Stress simulations for optimal mobility group IV p- and nMOS FinFETs for the 14 nm node and beyond
Author :
Eneman, Geert ; Brunco, D.P. ; Witters, L. ; Vincent, B. ; Favia, Paola ; Hikavyy, Andriy ; De Keersgieter, An ; Mitard, J. ; Loo, Roger ; Veloso, A. ; Richard, O. ; Bender, Hugo ; Lee, S.H. ; Van Dal, M. ; Kabir, N. ; Vandervorst, W. ; Caymax, M. ; Horig
Author_Institution :
Imec, Leuven, Belgium
Abstract :
Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond. Relaxed Ge p-FinFETs and even Ge with a GeSn5% source / drain stressor cannot outperform strained Si. However, growing the Ge channel strained on a SiGe75% strain relaxed buffer (SRB) provides a 49% mobility boost over strained Si. For Si n-FinFETs, SRB mobility boost is also possible, with Si on a SiGe 25% SRB improving mobility by 83%. Addition of a Si:C 2% S/D stressor increases that benefit to 109%. For Ge n-FinFETs, relaxed channels outperform strained Si by 120%, owing primarily to the 6× increase in fin sidewall mobility. Adding a SiGe 75% S/D stressor increases that benefit to 210%. In general, the SRB stressors have excellent scalability to future nodes. TCAD trends are qualitatively confirmed by Nano-Beam Diffraction.
Keywords :
Ge-Si alloys; MOSFET; carbon; semiconductor device reliability; technology CAD (electronics); S-D stressor; SRB mobility boost; Si:C; SiGe; TCAD; fin sidewall mobility; nMOS FinFET; nanobeam diffraction; optimal mobility group IV; pMOS FinFET; size 14 nm; source-drain stressor; strain relaxed buffer; stress enhanced mobilities; FinFETs; Logic gates; Silicon; Silicon germanium; Strain; Stress; Tin;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6478991