Low power parallel multiplier with column bypassing

Power management has become a great concern in VLSI design in recent years. In this paper, we present a low power parallel multiplier design, in which some columns in the multiplier array can be turned-off whenever their outputs are known. In this case, the columns are bypassed, and thus the switching power is saved. The advantage of this design is that it maintains the original array structure without introducing extra boundary cells, as did previous designs. Experimental results show that it saves 10% power for random inputs. Higher power reduction can be achieved if the operands contain more 0s than 1s. Compared with row-bypassing multipliers, this approach achieves higher power reduction with smaller area overhead.