DocumentCode
3543581
Title
Design of power-aware multiplier with graceful quality-power trade-offs
Author
Yen, Jieh-Hwang ; Dung, Lan-Rong ; Shen, Chi-Yuan
Author_Institution
Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2005
fDate
23-26 May 2005
Firstpage
1642
Abstract
A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions with regard to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for this purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency, subject to user-defined quality constraints, than full precision multiplication.
Keywords
low-power electronics; multiplying circuits; pipeline arithmetic; roundoff errors; controllable input precision; controllable output precision; graceful quality-power trade-off; lossy power-aware multiplier; multiplication precision; pipelined Dadda multiplier; power consumption/product precision trade-off; power limitations; rounding; trade-off efficiency; truncation; Batteries; Control engineering; Energy consumption; Energy resources; Finite impulse response filter; Hardware; IIR filters; Power dissipation; Power measurement; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464919
Filename
1464919
Link To Document