Quantitative and predictive model of reading current variability in deeply scaled vertical poly-Si channel for 3D memories

3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative for the 10nm nonvolatile memory technology node and beyond (1-2) provided that a significant drive current I_READ is delivered at a fixed reading gate voltage V_READ. Recently, we showed the discrete drops observed in the transfer characteristic (I_D vs. V_G) of 3D transistors (Fig. 1) are linked to single electron trapping in the highly defective poly-Si channel (3). This effect, in addition to low poly-Si mobility, results in low drain current measured in poly-Si channel transistors (4). As an immediate consequence, a large drain current I_D variability is observed in such deeply scaled devices (Fig. 1a). In order to develop a correct model predicting this I_D variability, both i) the charging component and ii) the intrinsic g_m-variability have to be separately characterized and physically understood to be afterwards correctly combined. The present abstract therefore aims at developing the methodology to predict the I_D distribution at fixed reading gate voltage V_READ by physical understanding of both effects: electron trapping and transconductance variations.