DocumentCode
3543715
Title
Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU
Author
Abe, Kiyohiko ; Noguchi, Hiroki ; Kitagawa, Eiji ; Shimomura, Naoharu ; Ito, Junichi ; Fujita, S.
Author_Institution
Corp. R&D center, Toshiba Corp., Kawasaki, Japan
fYear
2012
fDate
10-13 Dec. 2012
Abstract
This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).
Keywords
DRAM chips; MRAM devices; cache storage; D-MRAM-based cache memory; DRAM-MRAM hybrid memory design; LLC capacity; SRAM-based cache; advanced p-MTJ; current 50 muA; high performance mobile CPU; last level cache memory; power reduction; time 3 ns; ultrahigh speed write; Cache memory; Computer architecture; Magnetic tunneling; Mobile communication; Nonvolatile memory; Programming; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location
San Francisco, CA
ISSN
0163-1918
Print_ISBN
978-1-4673-4872-0
Electronic_ISBN
0163-1918
Type
conf
DOI
10.1109/IEDM.2012.6479019
Filename
6479019
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