Timing constraint specification and synthesis in behavioral VHDL

This paper describes two methods to specify timing constraints in behavioral VHDL for high-level synthesis purposes. The first method specifies timing constraints on sequences of statements by using predefined procedures. The second method provides support for specification of timing constraints across process borders based on concurrent assert statements on signal events. The paper discusses also an approach to synthesize hardware with timing constraints and concentrates in particular on how to ensure consistency between the behavior of the simulation model and that of the synthesized hardware