DocumentCode
3543884
Title
Combined frame memory architecture for motion compensation in video decoding
Author
Chang, Nelson Yen-Chung ; Chang, Tian-Sheuan
Author_Institution
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2005
fDate
23-26 May 2005
Firstpage
1806
Abstract
This paper proposes a combined frame memory architecture which is smaller in size and is potential in reducing power consumption compared to the most commonly used ping-pong frame memory. The combined frame memory maps both reference frame data and current frame data onto one single frame memory instead of two in ping-pong architecture. Together with the characteristic of high percentage of MB with zero-valued MV and no residual, the combined frame memory architecture is evaluated to be able to reduce not only the memory size, but also the average energy consumption and memory access latency for applications like surveillance, video telephony, and videoconferencing. According to the statistics and analysis results the proposed combined frame memory architecture memory size is only 57% compared to ping-pong architecture. The proposed combined frame memory architecture can reduce up to 83% of average latency and 39% of average power consumption compared to ping-pong frame memory architecture.
Keywords
decoding; memory architecture; motion compensation; power consumption; video coding; average energy consumption; combined frame memory architecture; current frame data; memory access latency; motion compensation; reduced power consumption; reference frame data; surveillance; video decoding; video telephony; videoconferencing; Cost function; Decoding; Delay; Energy consumption; Memory architecture; Motion compensation; Statistical analysis; Surveillance; Testing; Videoconference;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464960
Filename
1464960
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