Performance constrained floorplanning based on partial clustering [IC layout]

In this paper, we propose a partial clustered floorplanning method based on a corner block list (CBL) representation. The hierarchical strategies in this paper are designed for localizing the performance-constrained nets. We devise a sub CBL to represent the cluster and embed the sub CBL into the final CBL list. We combine the iterative optimization of the cluster packing into the annealing process. Therefore, the shape of the cluster can be optimized not only for the area and wirelength within the cluster, but also for the performance of the total packing. Our method can achieve a very stable performance and the feasibility of the final solution is guaranteed. Experimental results on an MCNC benchmark show the effectiveness of the method.