DocumentCode :
3544010
Title :
First experimental Ge CMOS FinFETs directly on SOI substrate
Author :
Cheng-Ting Chung ; Che-Wei Chen ; Jyun-Chih Lin ; Che-Chen Wu ; Chao-Hsin Chien ; Guang-Li Luo
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2012
fDate :
10-13 Dec. 2012
Abstract :
High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of Lchannel =120nm and Fin width=40nm with high Ion/Ioff ratio (>105), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S.S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of Lchannel =90nm exhibits a pretty well on-off behavior after forming gas annealing.
Keywords :
CMOS integrated circuits; MOSFET; annealing; silicon-on-insulator; CMOS FinFET; NFET; SOI substrate; SOI wafer; drain induced barrier lowering; gas annealing; n-channel FinFET; p-channel FinFET; size 120 nm; size 40 nm; size 90 nm; subthreshold swing; thin silicon on insulator; Aluminum oxide; CMOS integrated circuits; Films; FinFETs; Logic gates; Silicon; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0163-1918
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
Type :
conf
DOI :
10.1109/IEDM.2012.6479054
Filename :
6479054
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3544010
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