DocumentCode
3544037
Title
Fixed-outline floorplanning with constraints through instance augmentation
Author
Liu, Rong ; Dong, Sheqin ; Hong, Xianlong ; Kajitani, Yoji
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear
2005
fDate
23-26 May 2005
Firstpage
1883
Abstract
A new algorithm addressed to fixed-outline floorplanning is proposed. The proposed algorithm differs from general simulated annealing based algorithms in that it starts with a sub-instance (i.e. instance with fewer modules) of the given floorplanning instance and progressively augments the sub-instance until a feasible solution of the given instance is found. Experimental results show that the proposed algorithm is quite promising in fixed-outline floorplanning, even when tight outline and boundary and pre-placed constraints are imposed.
Keywords
circuit layout CAD; integrated circuit layout; system-on-chip; SOC designs; fixed-outline floorplanning; instance augmentation; simulated annealing; Computational modeling; Computer science; Data structures; Helium; Simulated annealing; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464979
Filename
1464979
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