Efficiency comparison between doubler and Dickson charge pumps

Author

Baderna, D. ; Cabrini, A. ; Torelli, G. ; Pasotti, M.

Author_Institution

Dipt. di Elettronica, Pavia Univ., Italy

fYear

2005

fDate

23-26 May 2005

Firstpage

1891

Abstract

The paper presents a comparison between two of the most popular charge pump structures, the Dickson charge pump and the cascade of voltage doublers. The comparison has been carried out considering power efficiency as the main parameter of interest. The discussion is supported by theoretical analysis and experimental results. To compare the two topologies, two voltage elevators were designed and integrated in a triple-well 0.18-μm CMOS technology. The two charge pumps were designed with the same operating clock frequency, the same storage capacitance per stage, and the same number of stages (and, thus, approximately the same area). The comparison showed that the voltage doubler has the higher power efficiency by about 13%.

Keywords

CMOS analogue integrated circuits; integrated circuit design; network analysis; voltage multipliers; 0.18 micron; CMOS technology; Dickson charge pump; clock frequency; power efficiency; storage capacitance; voltage doubler cascade; Boosting; CMOS technology; Capacitors; Charge pumps; DC-DC power converters; Elevators; Switches; Switching circuits; Topology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464981

Filename

1464981