Title :
VHDL based design methodology for hierarchy and component re-use
Author :
Kission, Polen ; Ding, Hong ; Jerraya, Ahmed A.
Author_Institution :
TIMA Lab., Grenoble, France
Abstract :
This paper presents a VHDL specification methodology aimed to extend structured design methodologies to the behavioral level. The goal is to develop VHDL modeling strategies in order to master the design and analysis of large and complex systems. Structured design methodologies are combined with AMICAL, a VHDL based behavioral synthesis tool, in order to allow hierarchical design and component re-use
Keywords :
VLSI; hardware description languages; integrated circuit design; logic CAD; logic design; specification languages; AMICAL; VHDL based behavioral synthesis tool; VHDL based design methodology; VHDL specification methodology; component re-use; hierarchical design; structured design methodologies; Circuit synthesis; Design automation; Design methodology; Hardware design languages; Laboratories; Logic circuits; Logic design; Registers; System analysis and design; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527446
