Novel μ-power log-domain integrators

This paper introduces novel CMOS bulk driven log-domain integrators using the CMOSP 0.18-μm process. The proposed design technique is based on the incomplete translinear loop (ITL). The integrators´ unique function is to cancel the slope factor n, which in turn results in: (1) reducing the biasing current, (2) reducing the power consumption, and (3) better time constant tenability. As an application, the integrators are used to design a 4th-order Chebyshev low-pass filter that can be tuned from 100 Hz to 10 MHz. The filter is biased by 300 nA, which corresponds to a tuned cut-off frequency of 1 MHz. The supply voltage is 1.8 V and the dynamic range is 50 dB for a PMOS prototype at THD 1%. The power consumption is 0.945 μW per pole.