DocumentCode
3544172
Title
Performance-efficient architecture for free-viewpoint 3DTV receiver
Author
Bondarev, E. ; Zinger, S. ; De With, P.H.N.
Author_Institution
Eindhoven Univ. of Technol., Eindhoven, Netherlands
fYear
2010
fDate
9-13 Jan. 2010
Firstpage
65
Lastpage
66
Abstract
This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.
Keywords
high definition television; television receivers; three-dimensional television; FPGA; HDTV; dual Virtex5; free-viewpoint 3DTV receiver; rendering algorithm; three-dimensional television; Cameras; Decoding; Field programmable gate arrays; Filling; Filtering; Filters; High definition video; Interpolation; Rendering (computer graphics); Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2010 Digest of Technical Papers International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
978-1-4244-4314-7
Electronic_ISBN
978-1-4244-4316-1
Type
conf
DOI
10.1109/ICCE.2010.5418923
Filename
5418923
Link To Document