DocumentCode
3544183
Title
Accuracy limitations of pipelined ADCs
Author
Quinn, Patrick J. ; Van Roermund, Arthur H M
Author_Institution
Xilinx, Dublin, Ireland
fYear
2005
fDate
23-26 May 2005
Firstpage
1956
Abstract
In this paper, the key characteristics of the main errors which affect the performance of a switched capacitor pipelined ADC are presented and their effects on the ADC transfer characteristics demonstrated. Clear and concise relationships are developed to aid optimized design of the pipeline ADC and error bounds are derived.
Keywords
analogue-digital conversion; circuit optimisation; pipeline processing; switched capacitor networks; transfer functions; accuracy limitations; error bounds; optimized design; performance; switched capacitor pipelined ADC; transfer characteristics; Capacitors; Charge transfer; Decoding; Design optimization; Equations; Fabrication; Logic; Pipelines; Throughput; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464997
Filename
1464997
Link To Document