DocumentCode
3544195
Title
Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs
Author
Quinn, Patrick J. ; Van Roermund, Arthur H M
Author_Institution
Xilinx, Dublin, Ireland
fYear
2005
fDate
23-26 May 2005
Firstpage
1964
Abstract
In this paper, an error analysis is presented to aid the design of a pipeline multi-bit front-end stage. It is demonstrated and quantified how the capacitor matching requirement can be reduced in high-resolution pipeline ADC. The paper continues by analyzing the optimal design for low power of the scaled back-end stages. Finally, a model is proposed to estimate the power per stage, and hence total power consumption of the pipeline ADC.
Keywords
analogue-digital conversion; circuit optimisation; error analysis; pipeline processing; power consumption; capacitor matching requirement; error analysis; high-resolution pipeline ADC; multi-bit front-end stage; optimization; power consumption; scaled back-end stages; CMOS process; Capacitors; Decoding; Design optimization; Energy consumption; Linearity; Pipelines; Redundancy; Signal resolution; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464999
Filename
1464999
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