DocumentCode :
3544202
Title :
Evolvable hardware with genetic learning
Author :
Higuchi, Tetsuya ; Iwata, Masaya ; Kajitani, Isamu ; Yamada, Hitoshi ; Manderick, Bernard ; Hirao, Yuji ; Murakawa, Masahiro ; Yoshizawa, Shuji ; Furuya, Tatsumi
Author_Institution :
Electrotech. Lab., Tokyo, Japan
Volume :
4
fYear :
1996
fDate :
12-15 May 1996
Firstpage :
29
Abstract :
This paper describes Evolvable Hardware (EHW) with genetic learning. EHW is hardware which is built on programmable logic devices (e.g. PLD and FPGA) and whose architecture can be reconfigured by using genetic learning to adapt to the new environment. There are two types of hardware evolutions; gate-level and function-level. As examples of gate-level evolution, a pattern recognition system and a welding robot controller are described. Then, function-level EHW is introduced. It is demonstrated that function-level hardware evolutions can attain high performances as in neural network applications (e.g. two spirals). New FPGA architecture for function-level evolution is also described
Keywords :
circuit optimisation; genetic algorithms; industrial robots; learning (artificial intelligence); neurocontrollers; pattern recognition; programmable logic devices; robot dynamics; FPGA; PLD; evolvable hardware; function-level evolution; gate-level evolution; genetic learning; hardware evolutions; neural network applications; pattern recognition system; programmable logic devices; spirals; welding robot controller; Control systems; Field programmable gate arrays; Genetics; Neural network hardware; Neural networks; Pattern recognition; Programmable logic devices; Robot control; Spirals; Welding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
Type :
conf
DOI :
10.1109/ISCAS.1996.541893
Filename :
541893
Link To Document :
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