DocumentCode
3544327
Title
Demonstration of scaled Ge p-channel FinFETs integrated on Si
Author
van Dal, M.J.H. ; Vellianitis, G. ; Doornbos, G. ; Duriez, Blandine ; Shen, T.M. ; Wu, C.C. ; Oxland, Richard ; Bhuwalka, K. ; Holland, Martin ; Lee, T.L. ; Wann, C. ; Hsieh, C.H. ; Lee, B.H. ; Yin, K.M. ; Wu, Z.Q. ; Passlack, Matthias ; Diaz, Carlos H.
Author_Institution
TSMC R&D, Leuven, Belgium
fYear
2012
fDate
10-13 Dec. 2012
Abstract
We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest gm/SS at Vdd=1V reported for non-planar unstrained Ge pFETs to date.
Keywords
III-V semiconductors; MOSFET; elemental semiconductors; germanium; silicon; ART; SCE control; aspect-ratio-tapping; bulk FinFET baseline; long-channel subthreshold swing; scaled Ge p-channel FinFET device; subthreshold characteristic; Current measurement; Epitaxial growth; FinFETs; Logic gates; Silicon; Temperature measurement; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location
San Francisco, CA
ISSN
0163-1918
Print_ISBN
978-1-4673-4872-0
Electronic_ISBN
0163-1918
Type
conf
DOI
10.1109/IEDM.2012.6479089
Filename
6479089
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