Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

Author

Schuddinck, P. ; Badaroglu, Mustafa ; Stucchi, Michele ; Demuynck, S. ; Hikavyy, Andriy ; Garcia-Bardon, M. ; Mercha, Abdelkarim ; Mallik, Abhidipta ; Chiarella, T. ; Kubicek, S. ; Athimulam, R. ; Collaert, Nadine ; Horiguchi, Naoto ; Debusschere, I. ; Th

Author_Institution

PT, Design & Technol. Enablement, IMEC, Leuven, Belgium

fYear

2012

fDate

10-13 Dec. 2012

Abstract

It is shown that the performance impact of middle-of-line (MOL) patterning process variations can be reduced by 30% by relaxing the standard cell gate pitch by 10% in both 20nm bulk planar (BPL) and 14nm bulk finFET (BFF). Tungsten can safely replace copper in local interconnect IM2, which allows the MOL critical dimensions (CD) to be reduced by 40% in 20nm BPL, resulting in 5% performance improvement. In 14nm BFF, 10% performance degradation can be traded in for 40% smaller IM1 contact area, allowing for a cell silicon footprint benefit of up to 20%.

Keywords

MOSFET; tungsten; MOL critical dimension; bulk finFET; bulk planar; cell silicon footprint; middle of line patterning process; size 14 nm; size 20 nm; standard cell gate pitch; standard cell level parasitics assessment; tungsten; Capacitance; Delay; Diamonds; High definition video; Logic gates; Power line communications; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4673-4872-0

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2012.6479101

Filename

6479101