Title :
Power consumption and performance of low-voltage bit-serial adders
Author :
Njolstad, Tormod ; Aas, Einar J.
Author_Institution :
Dept. of Phys. Electron., Norwegian Univ. of Sci. & Technol., Trondheim, Norway
Abstract :
By comparative simulations and chip measurements we have found that swing-restored pass transistor logic (SRPL) are suitable for low-power, low-voltage design. An enhanced SRPL full adder and a SRPL-compatible, double-edge-triggered D-type flip-flop are presented. These circuits may be simplified and jointly optimized when used in a bit-serial adder. A simulation model for finding the power consumption in bit-serial structures is discussed, and is used for comparing two bit-serial adder contestants, showing that these adders reduce the power consumption by a factor of two compared to a standard cell reference model
Keywords :
CMOS logic circuits; adders; digital arithmetic; logic design; D-type flip-flop; LV bit-serial adders; double-edge-triggered flip-flop; low-voltage adders; power consumption; simulation model; swing-restored pass transistor logic; Adders; Batteries; CMOS logic circuits; Circuit simulation; Delay; Energy consumption; Flip-flops; MOS devices; Semiconductor device measurement; Voltage;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541897
