Design considerations for a 10 GHz CMOS transmit-receive switch

Author

Naegle, Kristen M. ; Gupta, Subhanshu ; Allstot, David J.

Author_Institution

Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

2104

Abstract

A transmit-receive (T/R) switch is designed to operate at 10 GHz in a triple-well CMOS process. The transmit switch includes multiple parallel resonant networks to improve loss and isolation characteristics and the receive switch includes an impedance matching network and DC bias circuitry to increase linearity. A simple simulation model is proposed for linearity analysis of the receive switch. Finally, a figure-of-merit for T/R switches is proposed and used to compare previous published results.

Keywords

CMOS integrated circuits; impedance matching; integrated circuit design; linearisation techniques; microwave switches; nonlinear network synthesis; semiconductor switches; 10 GHz; CMOS transmit-receive switch; DC bias circuitry; figure-of-merit; impedance matching network; isolation characteristics; linearity analysis; loss characteristics; multiple parallel resonant networks; triple-well CMOS process; Analytical models; CMOS process; Circuit simulation; Impedance matching; Linearity; Propagation losses; RLC circuits; Resonance; Switches; Switching circuits; CMOS T/R switch; figure-of-merit; linearity analysis; triple-well CMOS process;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465034

Filename

1465034