Title :
A 0.9 V offset compensated FGMOS comparator
Author :
Rodriguez-Villegas, Esther
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll., London, UK
Abstract :
A novel low voltage low power fully differential comparator based on the floating gate MOS (FGMOS) operation is presented in this paper. The FGMOS transistor is used to increase the input range and compensate for offset variations simultaneously. The comparator operates with a supply voltage of 0.9 V in a 0.35 μm CMOS process. Its power consumption is less than 6.5 μW for an 11 MHz clock frequency.
Keywords :
CMOS integrated circuits; comparators (circuits); compensation; low-power electronics; 0.35 micron; 0.9 V; 11 MHz; CMOS process; FGMOS transistor; floating gate MOS; fully differential comparator; low power comparator; low voltage comparator; offset compensated FGMOS comparator; Capacitors; Clocks; Coupling circuits; Differential equations; Equivalent circuits; Fabrication; MOSFETs; Parasitic capacitance; Size control; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465048
