Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

Author

Lin, Dongyang ; Alian, A. ; Gupta, Swastik ; yang, Bo ; Bury, E. ; Sioncke, S. ; Degraeve, Robin ; Toledano, M.L. ; Krom, Raymond ; Favia, Paola ; Bender, Hugo ; Caymax, M. ; Saraswat, Krishna C. ; Collaert, Nadine ; Thean, A.

Author_Institution

IMEC vzw, Leuven, Belgium

fYear

2012

fDate

10-13 Dec. 2012

Abstract

High-Mobility n-MOSFET options with Ge and InGaAs channels are of intense interests. As the well-known interfacial trap (D_it) problem appears now contained, new challenges are emerging from above the interface. The evidence of oxide border traps (BT) in high-k dielectrics and its effect on the on-state performance of Ge and InGaAs n-MOSFETs are presented in this study through combined trap and transport analyses. The impact of the oxide traps on device frequency response and threshold voltage (V_th) stability could challenge the commercial realization of the high mobility channel MOSFET.

Keywords

III-V semiconductors; MOSFET; gallium arsenide; high-k dielectric thin films; indium compounds; Ge; InGaAs; frequency response; high mobility channel MOSFET; high-k dielectrics; interfacial trap problem; n-MOSFET; on-state performance; oxide border traps; threshold voltage stability; transport analyses; Charge carrier processes; Dispersion; Frequency measurement; Indium gallium arsenide; Logic gates; MOSFET circuits; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4673-4872-0

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2012.6479121

Filename

6479121