Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface

Author

Mandal, Gunjan ; Mandal, Pradip

Author_Institution

Alliance Semicond. (I) Ltd., Bangalore, India

fYear

2005

fDate

23-26 May 2005

Firstpage

2180

Abstract

This paper presents the design of a low voltage differential signaling (LVDS) receiver for a 1.3 Gb/s physical layer (PRY) interface. The receiver supports a wide input common mode range of 0.05 V to 2.35 V and a minimum input differential signal of 100 mV as specified by the IEEE LVDS standard. The design is implemented in 0.13 μm CMOS technology using both thick (3.3 V) and thin (1.2 V) gate oxide devices and the receiver consumes 11 mW of power. The receiver provides the interface between PHY and media access control (MAC) sub-layers.

Keywords

CMOS integrated circuits; data communication equipment; differential amplifiers; differential detection; low-power electronics; operational amplifiers; receivers; 0.05 to 2.35 V; 0.13 micron; 1.2 V; 1.3 Gbit/s; 100 mV; 11 mW; 3.3 V; CMOS; MAC sub-layers; OTA differential pairs; PHY interface; differential amplifier; input common mode range; low voltage differential signaling; low-power LVDS receiver; media access control sub-layers; minimum input differential signal; physical layer interface; thick gate oxide devices; thin gate oxide devices; Physical layer;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465053

Filename

1465053