A clock recovery circuit using half-rate 4×-oversampling PD

Author

Jang, Hyung-Wook ; Lee, Sung-Sop ; Kang, Jin-Ku

Author_Institution

Dept. of Electron. Eng., Inha Univ., Incheon, South Korea

fYear

2005

fDate

23-26 May 2005

Firstpage

2192

Abstract

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4× oversampling phase detector (PD) structure is described. The PD is designed by the 4× oversampling method. The PD finds the data-lead and data-lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. The proposed circuit is designed using the TSMC 0.25 μm CMOS technology and operating voltage is 2.5V. The circuit operates between 480 Mbit/s-1.5 Gbit/s.

Keywords

CMOS integrated circuits; buffer circuits; clocks; differential amplifiers; phase detectors; sampling methods; synchronisation; voltage-controlled oscillators; 0.25 micron; 2.5 V; 480 Mbit/s to 1.5 Gbit/s; TSMC CMOS technology; VCO; charge pump; clock recovery circuit; data lag; data lead; data recovery; differential buffer stages; differential clocks; half-rate 4×-oversampling PD; phase detector; serial link; CMOS technology; Charge pumps; Circuits; Clocks; Optical signal processing; Phase detection; Phase frequency detector; Sampling methods; Signal design; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465056

Filename

1465056