Title :
Digital built-in self-test of CMOS analog iterative decoders
Author :
Yiu, Mimi ; Gaudet, Vincent C. ; Schlegel, Christian ; Winstead, Chris
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
A design method is presented for testing of analog iterative decoders using digital built-in self-test (BIST). Mixed-signal BIST schemes are often complex and demand larger than acceptable hardware cost. By using a digital BIST scheme, analog iterative decoders can easily be tested in the digital domain. A BIST was designed and simulated for an (8,4,4) extended Hamming decoder using 0.18 μm CMOS. It is capable of detecting transistor faults in the decoder. A decoding rate of 444 kbps is achieved. The digital BIST scheme is suitable for any iterative decoder using the sum-product algorithm.
Keywords :
CMOS integrated circuits; Hamming codes; built-in self test; integrated circuit testing; iterative decoding; 0.18 micron; 444 kbit/s; BIST; CMOS analog iterative decoders; digital built-in self-test; extended Hamming decoder; sum-product algorithm decoder; transistor fault detection; Automatic testing; Built-in self-test; Circuit testing; Costs; Design methodology; Fault detection; Hardware; Iterative decoding; Iterative methods; Sum product algorithm;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465059
