Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs

Simulation-based verification is a popular method for functional validation of hardware. It is performed by applying a set of tests to the system under consideration and to its reference model, and comparing the results. The effectiveness of a test suite is measured by the fraction of the system covered by the tests. In this paper, we present a technique for selecting a part of the system, called checkpoints, with the property that any set of tests which covers the checkpoints covers the entire system. Thus, by constructing a test suit for the checkpoints, a 100% coverage can be achieved. We present a linear-time algorithm for computing a minimum checkpoint set based on pre- and post-dominator relations of the control flow graph of the HDL program representing the system.