DocumentCode
3544688
Title
Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices
Author
Shuto, Y. ; Yamamoto, Seiichi ; Sukegawa, H. ; Wen, Z.C. ; Nakane, Ryosho ; Mitani, Shinji ; Tanaka, Mitsuru ; Inomata, K. ; Sugahara, S.
Author_Institution
Imaging Sci. & Eng. Lab., Tokyo Inst. of Technol., Yokohama, Japan
fYear
2012
fDate
10-13 Dec. 2012
Abstract
The design and performance of pseudo-spin-MOSFETs (PS-MOSFETs) using nano-CMOS devices were computationally investigated. The operations of a PS-MOSFET with current-induced magnetization switching were also experimentally demonstrated by the hybrid integration of a vendor-made MOSFET and our-developed spin-transfer-torque magnetic tunnel junction. The nonvolatile SRAM and delay flip-flop applications of PS-MOSFETs were also examined.
Keywords
CMOS integrated circuits; MOSFET; SRAM chips; magnetic tunnelling; PS-MOSFET; current-induced magnetization switching; delay flip-flop applications; nanoCMOS devices; nonvolatile SRAM; our-developed spin-transfer-torque magnetic tunnel junction; pseudo-spin-MOSFET; vendor-made MOSFET; Computer integrated manufacturing; Integrated circuit modeling; Junctions; MOSFET circuits; Magnetic tunneling; Random access memory; Resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location
San Francisco, CA
ISSN
0163-1918
Print_ISBN
978-1-4673-4872-0
Electronic_ISBN
0163-1918
Type
conf
DOI
10.1109/IEDM.2012.6479131
Filename
6479131
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