DocumentCode
3544704
Title
Generating VHDL-A-like models using ABSynth
Author
Moser, V. ; Amann, H.P. ; Nussbaum, Pascal ; Pellandini, F.
Author_Institution
Inst. of Microtechnology, Neuchatel Univ., Switzerland
fYear
1995
fDate
18-22 Sep 1995
Firstpage
522
Lastpage
527
Abstract
A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced
Keywords
circuit analysis computing; formal specification; hardware description languages; ABSynth; VHDL-A-like models; analogue behavioural models; graphical specification; hardware description language; software tool; Circuit simulation; Code standards; Electronic circuits; Error correction codes; Hardware design languages; Iterative methods; Libraries; Packaging; Standards development; Synthesizers;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location
Brighton
Print_ISBN
0-8186-7156-4
Type
conf
DOI
10.1109/EURDAC.1995.527454
Filename
527454
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