Fully synthesizable delay cell design for emulation environment

This paper presents two fully synthesizable and emulation friendly delay cell designs that the authors have successfully implemented in a real emulation environment. Due to the analog nature of delay logics, none of the commercial emulators were able to support the actual delay behavior. Thus, manual additions of register were needed for each customized scenario. The effort required is huge and highly dependent on the complexity of the design. Both of these designs use conventional clock synchronous flip flops and simple logic gates to construct emulation friendly delay cell modules. The first design was constructed to support asynchronous based inputs while the latter design is capable of supporting various types of clock signals. Both of these two proposed designs have two parameters settings. The first parameter is used to configure the multiplier value of intended delay while the second parameter is used to configure the width of the input and output ports. These designs also require a reference clock, reset signal and user input to be connected to their input ports as well. The output from these designs is a delayed version of the user input. Finally the functionality of these designs have been verified on both simulation and emulation platforms.