Design of a wave-pipelined serializer-deserializer with an asynchronous protocol for high speed interfaces

Author

Hien, Bui Chinh ; Kim, Seok-Man ; Cho, Kyoungrok

Author_Institution

Dept. of Commun. & Inf. Eng., Chungbuk Nat. Univ., Cheongju, South Korea

fYear

2012

fDate

10-11 July 2012

Firstpage

265

Lastpage

268

Abstract

In this paper, we proposed an asynchronous wave-pipelined Serializer and Deserializer, or WP-SERDES in brief, that is totally clock-free. In contrast to conventional SERDES that employ power hungry phase-locked loops (PLLs) for synchronization in serializers and clock-data recovery (CDR) circuits in deserializers, the proposed WP-SERDES employs delay elements (DEs) consisting of inverter chains for timing reference. Besides, throughput of the proposed WP-SERDES is adjustable thanks to the voltage-controlled inverters used in the DEs. The proposed WP-SERDES which was simulated using 180nm CMOS process shows a 3.9 Gb/s throughput and 2.44 mW power consumption.

Keywords

CMOS digital integrated circuits; circuit simulation; clock and data recovery circuits; clocks; delay circuits; invertors; phase locked loops; CDR circuit; CMOS process simulation; DE; WP-SERDES; asynchronous protocol; asynchronous wave-pipelined serializer-deserializer; bit rate 3.9 Gbit/s; clock-data recovery circuit; delay element; high speed interface; inverter chain; power 2.44 mW; power consumption; power hungry PLL; power hungry phase-locked loop; timing reference; voltage-controlled inverter; Delay; Inverters; Phase locked loops; Propagation delay; Receivers; Synchronization; Throughput; SERDES; delay element; voltagecontrolled inverter; wave-pipelined;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ASQED), 2012 4th Asia Symposium on

Conference_Location

Penang

Print_ISBN

978-1-4673-2687-2

Type

conf

DOI

10.1109/ACQED.2012.6320513

Filename

6320513