DocumentCode :
3544769
Title :
Influence of machine model ESD stress on the failure thresholds of CMOS protection circuit elements
Author :
Lee, Mankoo
Author_Institution :
Sharp Microelectron. Technol. Inc., Camas, WA, USA
Volume :
4
fYear :
1996
fDate :
12-15 May 1996
Firstpage :
117
Abstract :
Machine Model (MM) failure thresholds have been investigated in CMOS protection circuit elements: both N-type and P-type devices of diode, punchthrough, Thick Field Oxide (TFO) transistor, and bulk transistor structures including the electro-thermal simulation and the characterization of Electro-Static Discharge (ESD) induced damage. This paper reports the interaction between electrical and thermal behaviors in CMOS input protection circuit simulations during MM ESD stress. Some observation are described as unique features in the MM ESD device characterization. For a channel length dependency, the MM ESD threshold failure voltage (Vesd) has bell-shaped curve for bulk transistors as well as almost constant value for TFO transistors
Keywords :
CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit modelling; protection; CMOS protection circuit element; ESD stress; N-type device; P-type device; TFO transistor; bulk transistor; diode; electrostatic discharge; electrothermal simulation; failure threshold voltage; machine model; punchthrough device; Biological system modeling; Breakdown voltage; Circuit simulation; Diodes; Electrostatic discharge; Immune system; Protection; Semiconductor device modeling; Switches; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
Type :
conf
DOI :
10.1109/ISCAS.1996.541914
Filename :
541914
Link To Document :
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