DocumentCode
3544787
Title
A resonant signal driver for two-phase, almost-non-overlapping clocks
Author
Athas, W.C. ; Svensson, L.J. ; Tzartzanis, N.
Author_Institution
Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
Volume
4
fYear
1996
fDate
12-15 May 1996
Firstpage
129
Abstract
We describe a driver circuit for reducing the power dissipated when driving heavily loaded signals such as the clock lines of a VLSI chip. The design exhibits good power efficiency across a wide range of frequencies. We have tested the driver with a prototype shift-register chip which had a clock line load in the hundreds of picofarads. The worst-case overall dissipation was 35% of fCV2 at 13 MHz and 5 V
Keywords
CMOS integrated circuits; VLSI; circuit resonance; clocks; driver circuits; integrated circuit design; shift registers; 13 MHz; 5 V; CMOS technology; VLSI chip; clock lines; heavily loaded signals; power dissipation reduction; power efficiency; resonant signal driver; shift-register chip; two-phase almost nonoverlapping clocks; worst-case overall dissipation; Clocks; Driver circuits; Frequency; Prototypes; Pulse circuits; Pulse generation; RLC circuits; Resonance; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541916
Filename
541916
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