Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

Author

Lee, Ki-Won ; Ohara, Yuki ; Kiyoyama, K. ; Konno, Shuji ; Sato, Yuuki ; Watanabe, Shigetaka ; Yabata, A. ; Kamada, Tomonari ; Bea, J.-C. ; Hashimoto, Hiroya ; Murugesan, Mariappan ; Fukushima, Tetsuya ; Tanaka, T. ; Koyanagi, Mitsumasa

Author_Institution

New Ind. Creation Hatchery Center (NICHe), Tohoku Univ., Sendai, Japan

fYear

2012

fDate

10-13 Dec. 2012

Abstract

We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

Keywords

CMOS image sensors; image processing; three-dimensional integrated circuits; ADC array chip; CMOS image sensor chip; TSV; analog circuit chip; chip-based 3D heterogeneous integration technology; high-speed 3D-stacked image processing; highly parallel 3D-stacked image processing; metal micro-bumps; parallel 3D-stacked image sensor; through-Si vias; Image processing; Image sensors; Prototypes; Silicon; Through-silicon vias; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4673-4872-0

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2012.6479156

Filename

6479156