Pre-capturing static pulsed flip-flops

The paper presents pre-capturing static pulsed flip-flops (PCSPFF), which are composed of a pulse generator and a static flip-flop with equal toggling delays. The pre-capturing technique makes PCSPFF faster than other high-performance flip-flops. Power consumption of the PCSPFF is observed to be the lowest among high-performance flip-flops. HSPICE simulation results at a frequency of 400 MHz show that the proposed PCSPFF exhibits power-delay-product reductions of 39.7% and 29%, respectively, compared to the hybrid-latch flip-flop and the conditional-capture flip-flop. Moreover, in practical circuits, the proposed PCSPFF shows power reduction of more than 50% and 32%, respectively, compared to the hybrid-latch flip-flop and conditional-capture flip-flop. A double-edge triggering feature can be added to the proposed flip-flops to reduce the clock frequency by 50%. Using double-edge triggering in the proposed flip-flops, an energy saving of 94% is achieved on the clock distribution network. Incorporating the double-edge triggering technique along with sharing pulse generation among flip-flops presents up to 68% power reduction in an 8-bit counter.