DocumentCode
3545050
Title
Efficient redundancy identification for test pattern generation
Author
Han, Sangyun ; Kang, Sungho
Author_Institution
Multimedia Processor Center, LG Semicon Co. Ltd., USA
fYear
1997
fDate
7-10 Sep 1997
Firstpage
52
Lastpage
56
Abstract
Due to the reconvergent fanouts which make the dependency among objectives and block the fault propagation, there may exist redundant faults in the circuits. This paper presents the isomorphism identification algorithm and the pseudo dominator algorithm which are used to identify redundant faults. Experimental results on ISCAS 85 benchmark circuits show that these algorithms are efficient in identifying redundant faults
Keywords
automatic test software; identification; integrated circuit testing; logic testing; redundancy; ATPG tool; isomorphism identification algorithm; pseudo dominator algorithm; redundancy identification; redundant faults; test pattern generation; Benchmark testing; Central Processing Unit; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Logic; Redundancy; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location
Portland, OR
ISSN
1063-0988
Print_ISBN
0-7803-4283-6
Type
conf
DOI
10.1109/ASIC.1997.616977
Filename
616977
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