A VLSI architecture for computing the optimal correspondence of string subsequences

The string matching problem arises in many fields of text analysis, image analysis and speech recognition. The computationally intensive nature of string matching makes it a candidate for VLSI implementation. Most of the existing algorithms and architectures for string matching consider strings that are from a finite alphabet set. The Optimal Correspondence of String Subsequence (OCS) problem, on the other hand, considers strings from an infinite alphabet set. This paper describes the design of a linear systolic array VLSI architecture for the OCS problem. The systolic solution for approximate string matching is modified and extended for the OCS problem in this paper. The architecture presented here can also be used to determine the minimum edit distance, the Longest Common Subsequence (LCS) and its length. The systolic architecture was simulated and verified using the Cadence design tools