An approach to the design of PFSCL gates

Author

Alioto, M. ; Fort, A. ; Pancioni, L. ; Rocchi, S. ; Vignoli, V.

Author_Institution

Dipt. di Ingegneria dell´´Informazione, Siena Univ., Italy

fYear

2005

fDate

23-26 May 2005

Firstpage

2437

Abstract

Design strategies for PFSCL (positive feedback source-coupled logic) gates are discussed. Criteria to size transistor aspect ratios and bias currents are derived as a function of the requirements on the noise margin and the power-delay trade-off, which are analytically modeled. The design criteria are also discussed in cases which are of practical interest, i.e., when a high speed or an optimum balance with power dissipation is required. The proposed design strategies are simple enough to be used in pencil-and-paper calculations. The theoretical results are validated through simulations on a 0.18-μm CMOS process.

Keywords

CMOS logic circuits; circuit feedback; delays; integrated circuit design; integrated circuit modelling; integrated circuit noise; logic gates; power consumption; semiconductor device models; 0.18 micron; CMOS process; analytical modelling; design strategies; positive feedback source-coupled logic gates; transistor aspect ratios; transistor bias currents; CMOS logic circuits; CMOS process; CMOS technology; Inverters; Logic design; Logic gates; MOS devices; Power dissipation; Signal to noise ratio; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465118

Filename

1465118