A non-iterative equivalent waveform model for timing analysis in presence of crosstalk

In the deep sub micron (DSM) regime, due to non-uniform scaling of interconnects, coupling capacitance between wires becomes an increasingly dominant fraction of the total wire capacitance. Crosstalk causes delay variations on signal lines and raises signal integrity problems. Including crosstalk in timing analysis has become imperative for current technologies. Existing timing analysis methods do not consider gate driving capability, output loading effects and waveform shape, and hence are not always accurate. We propose a non-iterative equivalent waveform model that addresses these issues.