Efficiency-oriented switching frequency tuning for a buck switching power converter

Successful on-chip integration of a buck switching power converter concurrently requires the fulfillment of stringent specifications, namely low silicon area occupancy, low relative output ripple, proper transient response, whilst assuring high efficiency. The paper focuses on efficiency optimization of a buck converter suited to CMOS integration. Switching and conduction energy loss models are discussed, both for continuous and discontinuous conduction modes. Minimization of overall power losses yields an optimum law that continuously tunes the switching frequency as a function of load current. A practical piecewise linear approximation is proposed and applied to transient simulations and to compute overall efficiency. The work concludes by comparing the efficiency-oriented optimum frequency tuning law to that intrinsically obtained from output voltage hysteretic control. Numerical examples consider a standard CMOS 0.35 μm technology.